Recovering the clock from a serial data stream traditionally uses Phase Locked Loops ( PLL ). Applications vary from RF Data Reception to reading the data off a Disc Drive's Magnetic Head.

The Problem with Serial Data...

Serial Data stream contains a series of 1's and 0's. However the streams will contain Sequential Groups of either 1's and 0's as shown below:

Therefore the question arises:

How do you tell how many 1s and 0s there
are if they appear next to each other?

The solution is firstly to Recover the Clock from the data and then use it to Sample the data to Extract the Individual data bits thus:

The true content of the data can then ascertained.

The method described below is also used within Universal Asynchronous Receiver Transmitters ( UARTs ). They traditionally have a Sampling Clock that is 16 Times the Data Rate.

The design can be implemented with ANY FPGA. However here I'm using the ALTERA MaxPlus II Graphical Design Tool. All the Circuits and Simulation Diagrams described in this document are extracted directly from Altera FPGA design files.

The Phase Locked Loop ( PLL ) contains a Free Running Voltage Controlled Oscillator ( VCO ) which is used to Phase Lock onto the data bits.

The Free Running attribute of a VCO is useful for when the incoming data pattern doesn't have a Phase Change i.e. a "0 to 1" or "1 to 0" transition for a while because of the data containing a series of sequential 1's or 0's.

TheVCO is Calibrated to Free Run at the Actual data rate during this time. When the next phase change does eventually occur some time later the VCO will again Phase Lock onto the data.

One of the VCO Clock Edges is then used to Sample the data to determine its actual content.

Intellectual Properties are used extensively within this design to Simply both the Explanation and Implementation.

Intellectual Properties ( IPs ) of Counters and Shift Registers are implemented using the ALTERA MaxPlus II Graphical Design Tool. They are also available in other packages and forms including VHDL.

CLICK HERE to access one of my other web pages where I discuss the Advantages and Uses of Intellectual Properties in detail.

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Data Generation

The Digital Clock Recovery design described is demonstrated using Pseudo-Random Data generated with the circuit shown below.

The circuit generates a 10 Stage Pseudo-Random or PN Data Sequence of 1023 states which is long enough to demonstrate the design's ability to recover the clock.

The CLOCK signal in the circuit below which creates the PN Data Sequence is Independent of the Edge Detection Circuit described later which recovers the clock that then is used to sample the data. This circuit simply Creates Data to demonstrate the Digital Clock Recovery concept.

An Edge Detection circuit is required to detect ALL the "0 to 1" and "1 to 0" Transitions of the incoming data. This is similar to a Phase Locked Loop device detecting Phase Changes.

The circuit needs to generate a Pulse from EITHER a "0 to 1" or a "1 to 0" Transition of the incoming data. This function can be seen operating in the Circuit Simulation section below with the EDGES signal representing the pulsed output.

The Traditional circuit using Descrete Logic Devices for generating the EDGES signal is a Pulse created from a Single Input Transition which is shown in the circuit below.

However this CAN'T be used within Programmable Logic Designs as when the compiler Minimises the design it decides that the 2 Inverter (NOT) Gates in series are Redundant and deletes them.

Unfortunately the Accumulated Propagation Delay of these gates are Crutial to the circuit operation and thus WON'T produce the expected Pulse on its output without them in circuit.

However the circuit below uses a Flip-Flop to create the output pulse which compilers WON'T minimise.

A Positive Edge on the Flip-Flop's Clock Input clocks in a LOGIC HIGH (VCC) from its D I/P. The LOGIC HIGH then propagates to the Flip-Flop's Q Output pin and thru the Inverter (NOT) Gate back to the Flip-Flop's Asynchronous Clear pin (CLRN)

This will then Asynchronously Reset the Flip-Flop but only AFTER the Combined Propagation Delay of the Inverter and the Flip-Flop has ocurred. This delay governs the Width of the final output pulse. This width will be Very Small but is wide enough to be used within the FPGA for the sampling circuit described later.

The circuit is shown below:

The circuit above generates a Pulse from a Positive Edge Transition on its I/P. However we need to detect BOTH Positive and Negative edges.

Therefore the circuit described below is required.

Each Flip-Flop is dedicated to detecting one type of edge. The Top Flip-Flop will create a pulse on a Negative Transition of the incoming data while the Bottom Flip-Flop will detect a Positive Transition.

The Rising or Positive Edge of the signal SAMPLE2 which is the MSB of the 3 Bit Sampling Counter shown below is used as the Sampling Point of the Pseudo Random Data described in the Data Generation section above. This is approximately in the Centre of the data bit.

The example below shows the Clock Signal (CLKX8) which represents a clock that is approximately 8 TIMES the Data Rate. This is created Independently of the PN Data clock.

The circuit will demonstrate that the actual Frequency of the sampling clock Isn't Critical. However the higher the Ratio of Sampling Data to Actual Data will give a more accurate Centre Position for the sampling process.

The simulation below demonstrates the circuit's ability to cope with Real Life situations where the 8 Times Sampling Frequency (CLOCK * 8) ISN'T exactly 8 times.

In fact the simulation sets the sampling frequency to 5% Higher than the 8 times. This is observed when the Sample Counter signal (SAMPLE COUNTER) sometimes gets Reset Early before its maximum count of 7 is reached.

• The PNDATA signal is the Pseudo Random Data from the PNOUT9 signal described in the Data Generation section above
  
  
• The CLOCK is clocking the PNDATA signal on its Positive Edge
  
  
• The PNOUT9 signal drives the Input to the Edge Detection Circuitry
  
  
• Both Positive and Negative edges are detected by the EDGES signal
  
  
• The EDGES signal described in the Edge Detection circuitry above is used to drive the Sampling Counter which is described in the Sampling Ciruitry section above
  
  
• The SAMPLE signal above is derived from the SIGNAL2 signal from the Sampling Ciruitry section above which was created by Another Flip-Flop Pulse Circuit described in the Edge Detection section above.
  
  
• The correct Sampling Position is determined within the PNDATA when the SAMPLE COUNTER signal has reached State 4
  
  
• This SAMPLE signal can then be used to Clock another D-Type Flip-Flop to Regenerate the Original Data
  
  
• The SAMPLE COUNTER sometimes gets Reset Early before the count of 7
  
  
• If there are Successive bits of the Same State the SAMPLE COUNTER Free-Runs and continues to sample the data correctly

The circuit above describes a purely Digital Method of Clock Recovery which traditionally used Phase Locked Loops which involved the Calibration of Analogue Components in a circuit.

The method described here isn't new as it is used inside all Universal Asynchronous Receiver Transmitters ( UARTs ) devices. However because UARTs are Ready Made and used widely there is no need for most designers to understand their internal Data Sampling Methods.

The design will sample the data bits exactly in the middle of each. However the design will function with up to 10% Error of the Sampling Frequency if there are Less Than 10 Successive Bits The Same. As described above this method relies on the clock to Free-Run reasonably accurately during the time when there are no Data Edges to resync it.

Thus a 10% Higher Sampling Frequency would mean that the Tenth Bit of a Continuous Stream of the Same data value in Succession would not be sampled correctly.

However a 5% margin of error IS acceptible as this is only 1 in 20 Bits. The standard UART uses a 10 bit Packet containing 1 Start Bit / 8 Data Bits / 1 Stop Bit. Therefore no sampling errors will occur.

Sampling rates of *16 are traditionally used within UARTs because their origins came from the era when it wasn't possible to achieve accurate and stable clocks. They use to suffer from Frequency Drift due to changes in temperature.